1. Field
This disclosure relates generally to flip flops, and more specifically, to flip flops having shared feedback.
2. Related Art
Flip flops are commonly used for data storage in a variety of different applications. For example, they may be used to build small on-chip memories such as queue buffers, where each flip flop stores a single bit of data. Typically each flip flop is implemented with both a master and a slave latch. Therefore, the complexity of a flip flop's structure and the number of transistors within each flip flop impacts various factors in the design and manufacture of an integrated circuit, such as design cost, test cost, and circuit area.
FIG. 1 illustrates one example of a prior art master-slave flip flop 10. Flip flop 10 includes an inverter 12, a transmission gate 14, a master latch 16 (which includes two inverters, one of which is a tri-state inverter), a transmission gate 18, a slave latch 20 (which includes two inverters, one of which is a tri-state inverter), and an inverter 22. The data input (D) of flip flop 10 is provided to an input of inverter 12, and an output of inverter 12 is provided to a first data terminal of transmission gate 14. A second data terminal of transmission gate 14 is coupled to a first node of master latch 16, and a second node of master latch 16 is coupled to a first data terminal of transmission gate 18 and second data terminal of transmission gate 18 is coupled to a first node of slave latch 20, and a second node of slave latch 20 is coupled to an input of inverter 22, and an output of inverter 22 is provided as the data output (Q) of flip flop 10. An inverted control terminal of transmission gate 14 receives a clock signal and a non-inverted control terminal of transmission gate 14 receives an inverted clock signal (which is an inverted version of the clock signal). An inverted control terminal of transmission gate 18 receives the inverted clock signal and a non-inverted control terminal of transmission gate 18 receives the clock signal. Also, an inverted control input of the tri-state inverter of master latch 16 receives the inverted clock signal and the non-inverted control input receives the clock signal. An inverted control input of the tri-state inverter of slave latch 20 receives the clock signal and the non-inverted control input receives the inverted clock signal.
In master-slave flip flop 10, when the clock signal is low (logic level 0), slave latch 20 stores the previous value of D (Dprevious) and provides this previous value via inverter 22 as Q, and transmission gate 18 is off. Also, when the clock signal is low, master latch is disabled (because the tri-state inverter is disabled) and transmission gate 14 is on. Therefore, the next value of D (Dnext) is propagated through inverter 12, transmission gate 14, and the enabled inverter of master latch 16. When the clock signal goes high (switches to logic level 1), transmission gate 14 is turned off and master latch 16 is enabled (because the tri-state inverter is again enabled by the clock signal) and latches the next value of D (Dnext). This next value of D is then propagated through transmission gate 18, the enabled inverter of slave latch 20 and inverter 22 and provided as output Q. (Note that slave latch 20 is disabled due to the tri-state inverter of the latch being disabled by the clock signal going high.) Therefore, just prior to a rising edge of the clock, the previous value of D (Dprevious) is continued to be provided at the output Q, and, at some propagation delay after the rising edge of the clock, the next value of D (Dnext) is provided at the output Q.